I was involved in a set of emails exchanged about per CPU data and atomic access. The argument was basically this
"If you access 64 bit data on a 32 bit machine, what part of the access is atomic?". One would assume that with per-CPU data, it is safe to read the data from a different CPU". The answer lies hidden in the processor architecture. Several RISC architectures require certain types of data to be aligned to specific boundaries (this in turn ensures that the access is atomic). Usually processor manuals suggest that data that is contained within a single cache line is likely to be fetched atomically. Ideally, it is recommended that the data be aligned to the boundary of it's size, so that access is atomic. To explain that further
16 bit data be aligned to a 16 bit boundary
32 bit data be aligned to a 32 bit boundary
64 bit data be aligned to a 64 bit boundary
So the next time you think of atomic access, data sizes, per CPU data, look at your processor manual and determine if the data needs to be protected when accessed from a different CPU.